Embodiments of the inventive subject matter generally relate to the field of circuit design, and, more particularly, to electronic design automation (EDA) tools to perform static checking of asynchronous clock domain crossings in a register transfer level (RTL) design of a chip or a system on a chip.
EDA tools are used to evaluate chip designs prior to fabrication. The EDA process broadly consists of two steps. The first step is a check of the RTL design logic. The second step is a creation of a physical circuit design from the RTL design. The first step, checking the design logic, can be referred to as RTL design checking. In RTL design checking, a language such as VHDL (Very High Speed Integrated Circuit Hardware Description Language) or Verilog can be used to describe and model the logical behavior of a circuit. RTL design checking itself can be decomposed into two steps: static checking, in which the structure of the design is analyzed without simulating its behavior; and dynamic checking, also referred to as verification, in which the behavior of the design is simulated or analyzed using formal verification techniques.
Asynchronous clock domain crossings (CDCs) are notorious for causing bugs and escapes in hardware designs, due to their difficulty in verifying pre-silicon. They are generally difficult to verify because their behavior is fundamentally nondeterministic and affected by physical delays, clock phase relationships, and possibly synthesis optimizations—things which are typically not modeled accurately in functional simulation environments.
Due to these problems, specialized tools have been developed, to analyze RTL designs, identify asynchronous crossings, characterize them, and sometimes graphically illustrate them. This allows a designer to review the crossings in a design, to determine if they are intentional or not. These tools will often attempt to verify the correctness of crossings as well. For example, a tool may perform static checks, which are checks that can be performed by the tool itself by merely analyzing the structure of the design.
Generally, however, conventional tools require manual intervention, to review and approve or disapprove of reported crossings, and filter out false failures. This is because current approaches typically attempt to infer the properties to be checked from commonly accepted “rules of thumb”, or by attempting to recognize “design patterns” within the design to determine designer intent. However, in real designs there are often legitimate exceptions made to these common rules or patterns.
Meanwhile, the number of asynchronous crossings has continued to grow on modern processor and system-on-chip (SoC) designs. For example, modern designs can have over 100,000 individual asynchronous crossing endpoints. This makes any approach that requires manual intervention more expensive and more likely to impact project schedules.